The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods of lithographic patterning to form interconnect structures for a chip.
A back-end-of-line (BEOL) interconnect structure may be used to electrically couple device structures fabricated on a substrate during front-end-of-line (FEOL) processing. The BEOL interconnect structure may be formed using a dual-damascene process in which via openings and trenches etching in a dielectric layer are simultaneously filled with metal to create a metallization level. In a via-first, trench-last dual damascene process in which via openings are formed in a dielectric layer and then a trench is formed in the dielectric layer above the via openings, the via openings are unfilled during the etching process forming the trenches. In a single-damascene process, the via openings and trench are formed in different dielectric layers and filled separately with metal.
Dry etch processes are commonly used to fabricate trenches and vias during dual-damascene processing involving copper and a low-k dielectric material. As the semiconductor device technology node advances to smaller dimensions, the decreasing size of semiconductor devices increased the difficulty of controlling the profile of vias and trenches. Metal hardmasks have been utilized to improve etch selectivity to low-k dielectric materials and, thereby, to improve profile control. As feature sizes shrink in advanced semiconductor device technology nodes to 7 nm and below, the ability to form features in a low-k dielectric material with multi-patterning techniques becomes increasingly more challenging.
Improved methods of lithographic patterning to form interconnect structures for a chip are needed.